4 mega bit 3.3 volt high speed sram dp3s128x32y5 ad vanced in for ma tion de scrip tion: the dp3s128x32y5 is the 128k x 32 sram module the utilize the new and innovative space saving tsop stacking technology. the module is constructed of four 128k x 8 sram?s that are configured as 128k x 32. the dp3s128x32y5 provides for a compatible upgrade path to lower density compatible modules. the module features high speed access times with common data inputs and outputs. fea tures: ? organizations available: 128k x 32, 256k x 16 or 512k x 8 ? access times: 10, 12, 15ns ? fully static operation - no clock or refresh required ? single +3.3v power supply, 10% tolerance ? ttl compatible ? common data inputs and outputs ? package: 64-pin tsop stack 30a236-04 rev. a 1 pin-out di a gram p i n 1 i n d e x ( t o p v i e w ) a 0 1 a 1 2 4 7 a 2 3 4 6 a 3 4 4 5 a 1 6 a 4 5 4 4 a 1 5 c s 0 6 4 3 o e i / o 0 7 4 2 i / o 7 i / o \ 1 8 4 1 i / o 6 v d d 9 4 0 v s s v s s 1 0 3 9 v d d i / o 2 1 1 3 8 i / o 5 i / o 3 1 2 3 7 i / o 4 w e 1 3 3 6 a 1 4 a 5 1 4 3 5 a 1 3 a 6 1 5 3 4 a 1 2 a 7 1 6 3 3 a 1 1 a 8 a 1 0 a 9 3 2 func tional block di a gram 4 meg based, 10 - 15ns, lp-stack 30a236-04 a this document contains information on a product under consideration for development at dense-pac microsystems, inc. dense-pac reserves the right to change or discontinue information on this product without prior notice. pin names a0 - a16 address i/o0 - i/o31 data input / output ce 0 - ce 3 low chip enables we write enable oe output enable v dd power (+3.3v) vss ground n.c. no connect
dp3s128x32y5 dense-pac microsystems, inc. ad vanced in for ma tion dc operating characteristics: over operating ranges symbol characteristics test condition min. max. unit i in input leakage current v in = 0v to v dd -8 +8 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih or we = v il -2 +2 m a i cc operating supply current cycle = min., duty = 100%, i out = 0ma x8 355 ma x16 450 x32 640 i sb1 full standby standby current v in 3 v dd -0.2v or v in v ss +0.2v 180 ma i sb2 standby current ( ttl ) ce = v ih 260 ma v ol output low voltage i ol = 8.0ma 0.4 v v oh output high voltage i oh = -4.0ma 2.4 v note: typical measurements made at +25 c. cycle = min., v dd = 5.0v. 30a236-04 rev. a 2 recommended operating range 3 symbol characteristic min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 v dd +0.3 v v il input low voltage -0.3 2 0.8 v t a operating temperature c 0 +25 +70 o c ci -40 +25 +85 capacitance 4 : t a = +25 o c, f = 1.0mhz symbol parameter max. unit condition c adr address input 35 pf v in 2 = 0v c ce chip enable 15 c we write enable 35 c oe output enable 35 c i/o data input/output 15 ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns* input and output timing reference levels 1.5v output load load c l parametric measured 1 30pf except t lz , t hz , t ohz , t olz and t whz 2 5pf t lz , t hz , t ohz , t olz and t whz truth table mode ce n we oe i/o pin supply current not selected h x x high-z standby d out disable l h h high-z active read l h l d out active write l l x d in active h = high l = low x = don?t care absolute maximum rating 3 symbol parameter max. unit t stc storage temperature -65 to +150 o c t bias temperature under bias -55 to +125 o c v dd supply voltage 1 -0.5 to +4.6 v v i/o input/output voltage 1 -0.5 to +4.6 v dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -4ma 2.4 v v ol low voltage i ol =8ma 0.4 v figure 1. output load * including probe and jig capacitance. +3.3v 319 w 353 w c l * d out
dense-pac microsystems, inc. dp3s128x32y5 ad vanced in for ma tion ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 10ns 12ns 15ns unit min. max. min. max. min. max. 1 t rc read cycle time 10 12 15 ns 2 t aa address cycle time 10 12 15 ns 3 t co chip enable access time 10 12 15 ns 4 t oe output enable to output valid 5 6 7 ns 5 t clz chip enable to output in low-z 4, 6 3 3 3 ns 6 t olz output enable to output in low-z 4, 5 0 0 0 ns 7 t chz chip enable to output in high-z 4, 5 0 5 0 6 0 7 ns 8 t ohz output enable to output in high-z 4, 5 0 5 0 6 0 7 ns 9 t oh output hold from address change 3 3 3 ns ac operating condition and characteristic read cycle: over operating ranges 6, 7 no. symbol parameter 10ns 12ns 15ns unit min. max. min. max. min. max. 10 t wc write cycle time 10 12 15 ns 11 t aw address valid to end of write 8 9 10 ns 12 t cw chip enable to end of write 8 9 10 ns 13 t sa address setup time * 0 0 0 ns 14 t wp write pulse width ( oe high) 8 9 10 ns 15 t wp1 write pulse width ( oe low) 10 12 14 ns 16 t wr write recovery time 0 0 0 ns 17 t whz write enable to output in high 4, 5 0 5 0 6 0 7 ns 18 t dw data to write time overlap 6 6 7 ns 19 t dh data hold time form write time 0 0 0 ns 20 t ow output active from end of write 4, 5 3 3 3 ns * valid for both read and write cycles. 30a236-04 rev. a 3 read cycle 1: ad dress con trolled we is high ce and oe are low. address data i/o
dp3s128x32y5 dense-pac microsystems, inc. ad vanced in for ma tion 30a236-04 rev. a 4 read cycle 2: ce is con trolled. we is high. write cycle 1: oe clock. address ce oe data i/o address ce ce we data in data out
dense-pac microsystems, inc . dp3s128x32y5 ad vanced in for ma tion 30a236-04 rev. a 5 write cycle 2: oe is low. address ce we data in data out write cycle 3: ce con trolled. address ce we data in data out
dp3s128x32y5 dense-pac microsystems, inc. ad vanced in for ma tion note: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specification is not implied. exposure t o absolute maximum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. transition is measured at the point of 500mv from steady state voltage. 6. when oe and ce are low and we is high, i/o pins are in the output state, and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. 8. ce and we can initiate and terminate write cycle. 30a236-04 rev. a 6 or dering in for ma tion wave form key data valid transition from transition from data undefined high to low low to high or don?t care
dense-pac microsystems, inc. dp3s128x32y5 ad vanced in for ma tion dense-pac microsystems, inc. 7321 lincoln way, garden grove, california 92841-1431 (714) 898-0007 u (800) 642-4477 u fax: (714) 897-1772 u http ://www.dense-pac.com 30a236-04 rev. a 7 me chan i cal drawing
|
